1. Field of the Invention
The present invention relates generally to semiconductor integrated circuit devices having a plurality of internal circuits having different supply voltages, and more particularly to the technology for protecting active elements in such internal circuits from failure due to electrostatic discharge or the like.
The semiconductor integrated circuit devices directed by the present invention may include a multi-functional LSI (large scaled integrated circuit device), a digital/analog hybrid LSI, a digital LSI for multi-power supply, to name a few.
2. Description of Technical Background
FIGS. 10A and 10B illustrate a typical layout of a semiconductor integrated circuit device, fabricated on a single chip, which has a plurality of internal circuits using different power lines, wherein FIG. 10A is a schematic diagram generally illustrating the layout of the chip, and FIG. 10B is a circuit diagram of a main portion. FIGS. 11A to 11E illustrate at an element level portions of the internal circuits which communicate signals therebetween, wherein FIG. 11A is a detailed circuit diagram; FIG. 11B is a layout diagram of semiconductor regions; FIG. 11C is a layout diagram of the semiconductor regions in which gates and power lines have also been patterned; FIG. 11D is a layout diagram of the semiconductor regions in which signal wires have further been patterned; and FIG. 11E is a vertically sectioned perspective view illustrating a semiconductor region and a gate which constitute a basic cell or a basic unit for an active element. It should be noted that in FIG. 11D, thick solid lines indicate signal wires; black circles indicate connections such as contact holes at which signal wires extend deep into a semiconductor layer; and small squares indicate connections at which signal wires extend into a power line layer but not to the underlying semiconductor layer. The same legends are applied to FIGS. 1B, 2B, 4B, 5B and 8A, later described.
The generalization of manufacturing processes, automated designs and so on have been developed for large scaled integrated circuits, which are applied in a wide variety of products, for example, gate arrays, custom LSIs, ASICs (Application Specific IC), and so on, on the assumption of the common utilization of basic cell structures, regular layouts and so on. In many cases, external connection terminals, external signal input/output circuits, and internal circuits are arranged in order from the periphery to the center of a semiconductor integrated circuit device. As described herein as a typical example, a semiconductor integrated circuit device 1 (see FIG. 10A) includes an internal circuit 4A and an internal circuit 4B which are supplied with different supply voltages, so that these internal circuits 4A, 4B are positioned separately in a left-hand and a right-hand block. Also, a left-hand external signal input/output circuit 3A and some external connection terminals 2 on the left side, located near the left-hand internal circuit 4A, are generally connected to the internal circuit 4A, and are adapted to relay signals associated with the internal circuit 4A to the outside and to supply power to the internal circuit 4A. Remaining external signal input/output circuit 3B and external connection terminals 2, in turn, are generally connected to the internal circuit 4B, and are adapted to relay signals associated with the internal circuit 4B to the outside and to supply power to the internal circuit 4B.
A variety of combinations of supply voltages fed to these internal circuits 4A, 4B may be contemplated, for example, 12 volts and 5 volts; 5 volts and 3 volts; 3 volts and 2 volts, and so on. In the drawings, circuits fed with a relatively higher supply voltage (left-hand ones in FIG. 10A), elements contained therein, and so on are designated by reference numerals followed by “A,” while circuits fed with a relatively lower supply voltage (right-hand ones in FIG. 10B), elements contained therein, and so on are designated by reference numerals followed by “B.” The same rule is applied also to FIGS. 12A to 12C and FIGS. 1A to 9, later described.
In such combinations, powering of the internal circuit 4A from the outside requires at least one pair of power lines, for example, a power line 8A for applying a positive voltage and a power line 9A for grounding, so that at least one of multiple external connection terminals 2 is assigned as a high power terminal 5A which is connected to the one power line 8A, and at least one of the remaining external connection terminals 2 is assigned as a ground terminal 6A which is connected to the other power line 9A. The power lines 8A, 9A individually extend as circular, tree-like, or stripe wires (see FIG. 10A), not shown, and are connected to an input protection circuit 3AA in the external signal input/output circuit 3A, and are further routed therethrough to the internal circuit 4A in which they are also connected to multiple internal elements 11A, 12A, 13A (see FIG. 10B).
The input protection circuit 3AA (see FIG. 10B) is provided for a connection line which connects an input/output terminal 7A assigned to an input to the internal element 11A or the like of the external connection terminals 2 to a connection line with the internal element 11A. Typically, the input protection circuit 3AA may be composed of a pair or a set of rectifying elements such as diodes, transistors or the like, connected to the connection line and to the power lines 8A, 9A. If surge noise (ESD surge: Electrostatic Discharge) such as static electricity introduces into the input/output terminal 7A, the input protection circuit 3AA forces the surge noise to escape to the high power terminal SA or the ground terminal 6A to protect the internal element 11A from the surge noise.
Likewise, in the internal circuit 4B (see FIGS. 10A, 10B), although repetitive details are omitted, a power line 8B for applying a positive voltage lower than that of the power line 8A is routed from a lower power terminal 5B through an external signal input/output circuit 3B to the internal circuit 4B, while a power line 9B for grounding, forming a pair with the power line 8B, is likewise routed from a ground terminal through the external signal input/output circuit 3B to the internal circuit 4B. These lines are connected to an input protection circuit 3BB in the external signal input/output circuit 3B, as well as to internal elements 11B, 12B, 13B in the internal circuit 4B, and a connection line from the input/output terminal 7B to the internal element 11B is connected to the input protection circuit 3BB. All of these power lines or at least the power lines 8A, 8B may be indirectly connected through the protection circuit or the like but will never be directly connected or short-circuited within the semiconductor integrated circuit device 1, so that the internal circuit 4A, 4B act as a plurality of individual internal circuits using different power lines.
Further, as can be seen in FIG. 10B, for communicating signals between the internal circuits 4A, 4B, inter-circuit signal wires 12 for interconnecting the output element 12A of the internal circuit 4A and the input element 12B of the internal circuit 4B, and inter-circuit signal wires 13 for interconnecting the output element 13B of the internal circuit 4B and the input element 13A of the internal circuit 4A are also routed between the internal circuits 4A, 4B as many number of lines as required for communicating signals.
The output element 12A may comprise a single or a plurality of active elements such as transistors. For example, if the output element 12A is a CMOS inverter (see FIG. 11A), the output element 12A includes a p-type MOS (hereinafter called the “pMOS”) transistor 12AP having a source connected to the power line 8A, a drain connected to the inter-circuit signal wire 12, and a gate connected to an internal signal wire SA within the internal circuit 4A; and an n-type MOS (hereinafter called the “nMOS”) transistor 12AN having a source connected to the power line 9A, a drain connected to the inter-circuit signal wire 12, and a gate connected to the internal signal wire SA within the internal circuit 4A. The input element 12B also includes a pair of transistors, pMOS transistor 12BP and NMOS transistor 12BN, having their sources connected to the power lines 8B, 9B, respectively, which have their gates connected to the inter-circuit signal wire 12, and their drains connected to an internal signal wire SB within the internal circuit 4B.
The input element 13A and the output element 13B, though signals are communicated in directions opposite to each other, each includes a similar transistor pair consisting of one pMOS transistor (13AP, 13BP) and one nMOS transistor (13AN, 13BN), with their drains or gates connected to the inter-circuit signal wire 13.
Each of the transistors 12AP, 12AN, 12BP, 12BN (and the transistors 13AP, 13AN, 13BP, 13BN) is an active element connected to the inter-circuit signal wires in a first connection configuration. Then, for fabricating the semiconductor integrated circuit device 1 having the circuits as mentioned above on a silicon wafer or the like (see FIGS. 11B to 11E), miniature basic cells for active elements are repeatedly arranged at regular pitches in the vertical and horizontal directions in regions allocated to the internal circuits 4A, 4B in each chip. For example, a basic cell for a CMOS (see FIG. 11B) is composed of an nMOS cell and a pMOS cell. The NMOS cells are distributed on a p-type substrate (p-Sub) in the form of island, and an n-type semiconductor region, a gate oxide film region, and an n-type semiconductor region may be formed for each of the cells. Alternatively, n-type semiconductor regions, gate oxide film regions, n-type semiconductor regions, gate oxide film regions and n-type semiconductor regions may often be previously formed as illustrated, and a central n-type semiconductor region is shared to fabricate two n-type MOS transistors.
The pMOS cells, in turn, are distributed likewise in the form of island in a n-type well region (n-Well) and positioned to establish a one-to-one correspondence to the nMOS cells, and are implemented by replacing the n-type semiconductor region in the nMOS cells with a p-type semiconductor region. Then, on a gate oxide film region of each basic cell, an isolated pattern made of a metal or the like is individually formed to provide a gate and its lead-out (see FIG. 11E). Further, another conductive layer made of a metal, overlying a suitable insulating layer or the like interposed therebetween, is patterned to form the power line 8A on a sequence of pMOS basic cells in the internal circuit 4A; the power line 9A on a sequence of nMOS basic cells in the internal circuit 4A; the power line 8B on a sequence of pMOS basic cells in the internal circuit 4B; and the power line 9B on a sequence of NMOS basic cells in the internal circuit 4B (see FIG. 11C).
In this way, the basic cells for active elements are regularly arranged in the same structure or similar structure until the midway of pre-processing of the semiconductor process to provide highly generalized wafers.
Subsequently, as a specific allocation of active elements is determined based on a particular application, for example, the active elements 12AP, 12AN in the first connection configuration are allocated to adjacent basic cells in the internal circuit 4A (see FIG. 11C), while the active elements 12BP, 12BN in the first connection configuration are likewise allocated to adjacent basic cells in the internal circuit 4B. Consequently, necessary wires associated with these active elements are substantially uniquely determined in the following manner.
Specifically, as can be seen in FIG. 11D, basic cells of interest are formed with contact holes (see a black line in FIG. 11D) such as via holes at the centers thereof to connect the sources of the active elements 12AP, 12AN, 12BP, 12BN in the first connection configuration to the power lines 8A, 9A, 8B, 9B, respectively. In the internal circuit 4A, the internal signal wire SA is connected to the gate of the active element 12AP in the first connection configuration as well as to the gates of both the active elements 12AP, 12AN in the first connection configuration. Also, one end of the inter-circuit signal wire 12 is branched and connected to the drains of the active elements 12AP, 12AN in the first configuration at corners of the basic cells.
The other end of the inter-circuit signal wire 12 extends into the internal circuit 4B and is connected to the gate of the active element 12BP in the first connection configuration. In the internal circuit 4B, the active elements 12BP, 12BN in the first connection configuration have their gates connected to each other. The internal signal wire SB has its one end branched and connected to the drains of the active elements 12BP, 12BN in the first connection configuration at corners of the basic cells. The branched signal wires are again joined and connected to another internal element or the like in the internal circuit 4B.
In this way, the basic semiconductor parts are generalized and utilized in common, and a variety of circuits are implemented by changing the allocation of active elements, determined subsequent to the formation of the basic semiconductor parts, and the wiring formed on an overlying layer and so on, thereby making it possible to rapidly and precisely respond to a variety of applications.
3. Prior Art
Conventionally, the semiconductor integrated circuit device 1 as described above is provided with an inter-block protection circuit between both the internal circuits 4A, 4B in addition to the aforementioned input protection circuits 3AA, 3BB, as countermeasures to the electrostatic breakdown. Such an inter-block protection circuit is composed of resistors, rectifying elements, zener diodes or transistors having a similar function, and so on, and is also connected to the power lines 8A, 8B, 9A, 9B on which different supply voltages are fed.
As increasing miniaturization of internal circuits results in lower resistance of internal elements to electrostatic breakdown, the protection against the electrostatic breakdown has been enhanced by enlarging the input protection circuits which are smaller in number than internal elements, and by increasing the number of inter-block protection circuits or enlarging the inter-block protection circuit.